ID:10246 Verilog HDL Module Instantiation error at <location>: Module Instance Parameter Value Assignment list cannot assign parameter values by both name and order

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you used a Module Instance Parameter Value Assignment list to assign values to the parameters of a module instance. However, in the list, you used both assignment by order and assignment by name. These two assignment methods are mutually exclusive; that is, parameter assignments in a Module Instance Parameter Value Assignment list shall be solely by order or solely by name.

ACTION: Choose a consistent method for making parameter assignments in a Module Instance Parameter Value Assignment list.