ID:10156 Verilog HDL error at <location>: variable "<name>" is not an array of vectors

CAUSE: In a Verilog Design File (.v) at the specified location, you used too many indexes with a multidimensional array. For example, the following excerpt of a sample Verilog HDL design shows code that could cause this error:

   reg mem[7:0][7:0];
   always @(clk) begin
      out = mem[in_a][in_b][in_c];
      mem[in_a][in_b] = in_c;
   end

            

However, the Quartus Prime software does not support synthesis of multidimensional arrays. If you fix this error, you will still receive an unsupported feature error for using a multidimensional array.

ACTION: Edit the design to remove the use of multidimensional arrays. As an alternative, you may want to use a memory, which is an array of vectors and can be declared as shown in the following example:

reg [n:0] my_memory[m:0]