ID:10279 Verilog HDL Port Declaration error at <location>: <direction> port(s) cannot be declared with type "<type>"

CAUSE: In a Verilog Design File (.v), you declared ports with a type that is incompatible with the specified port direction. In Verilog HDL, input and inout ports must have a Net type, and output ports must have a Net type or an Output Variable type, for example "time" or "integer".

ACTION: Specify a legal type for the specified port direction.