ID:10278 Verilog HDL Port Declaration error at <location>: <direction> port "<name>" cannot be declared with type "<type>"

CAUSE: In a Verilog Design File (.v), you redeclared the specified port with a type that is incompatible with the specified direction of the port. In Verilog HDL, input and inout ports must have a Net type. Output ports must have a Net type or an Output Variable type, for example "time" or "integer".

ACTION: Specify a legal type for the specified port.