ID:10152 Verilog HDL Variable Declaration error at <location>: variable name "<name>" is already used

CAUSE: In a Verilog Design File (.v) at the specified location, you declared the specified variable name, but the name is already defined elsewhere in the design. For example, you may have used the same name for a wire and for a module instantiation. All identifiers within a single module must have unique names.

ACTION: Choose a new name for the variable.