ID:10114 Verilog HDL Gate Instantiation error at <location>: name-based port connection is not allowed in Gate Instantiation

CAUSE: In a Gate Instantiation at the specified location in a Verilog Design File (.v), you specified connections by using named ports. The Quartus Prime software does not support name-based port connections in Gate Instantiations.

ACTION: Edit the design to make sure the output ports are the first argument in the Gate Instantiation, followed by the input ports, as shown in the following example:

g = xor(out, in1, in2)