ID:10045 Verilog HDL error at <location>: value cannot be assigned to constant

CAUSE: In a Verilog Design File (.v) at the specified location, you assigned a value to a constant wire; however, assignments to constants are not allowed. This error may occur if, for example, w is declared as wire [1:0] and you assign w[2] = 1;.

ACTION: Edit the design so the data type and bus width are correct and do not create an assignment to a constant.