ID:10666 Bidirectional ports "<name>" and "<name>" at <location> directly or indirectly feed each other

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you declared the specified bidirectional ports. Later, you assigned these bidirectional ports to each other using multiple directional assignments, e.g. b1 <= b2. You most likely intended to create a bidirectional connection between the two ports, but you cannot create such a connection in Verilog or VHDL using directional assignments. For example, the following VHDL fragment assigns bidirectional port b2 to the bidirectional port b1 in one assignment, and then it assigns b1 to b2 in another.

ENTITY example IS
   PORT
   (
      b1 : INOUT   BIT;
      b2 : INOUT   BIT
   );
END example;

               
ARCHITECTURE a OF example IS
BEGIN
   b2 <= b1;
    b1 <= b2;
 END a;