ID:10113 Output port "<name>" on instance "<name>" at <location> cannot be driven by constant <name>

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you connected the specified output port on the specified instance to a constant. This electrical conflict often results from unintentional errors in the port map (VHDL) or port connection list (Verilog).

ACTION: Redeclare the specified port as an input or an inout (bidirectional) port, which will resolve the electrical conflict. You can also resolve the conflict by connecting the port to a non-constant net.