ID:10031 Net "<text>" at <location> is already driven by input port "<text>", and cannot be driven by another signal

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd) at the specified location, you declared a signal. Later, you assigned to the signal the values of both an input port and a different signal in the same Verilog HDL module or VHDL entity. These conflicting assignments create an electrical conflict on the specified net, which Quartus Prime Integrated Synthesis created to represent the original signal. The conflict must be resolved before the Quartus Prime software can continue processing the design. The message immediately below this message indicates the input port's declaration.

ACTION: Check the Verilog HDL module or VHDL entity to locate conflicting assignments to the same signal. Remove all but one of the assignments.