ID:10904 SystemVerilog error at <location>: <name> type and <name> type do not match - <string>

CAUSE: In an expression, assignment, port connection, or argument binding, you used two objects with the specified types. Based on the context, SystemVerilog requires the objects to have matching types, but these two types do not match for the reason(s) listed in the message. Matching types is the strictest form of type compatibility defined by the SystemVerilog language. Enums and structs only match themselves. That is, an enum type from one declaration can never match an enum type from another declaration. Unpacked arrays only match unpacked arrays with the same shape and matching base types. Packed arrays and other integral types match only if they have the same dimensions, bounds, signing, and two-state or four-state logic types.

ACTION: Modify your HDL source to remove the type error. You may need to modify your expression or the declarations of the objects themselves.