ID:10166 SystemVerilog RTL Coding error at <location>: always_comb construct does not infer purely combinational logic.

CAUSE: In an always construct at the specified location in a Verilog Design File(.v), you indicated that you were describing combinational logic by using the always_comb keyword. However, Integrated Synthesis inferred one or more latches when synthesizing the statements in this construct. Most likely, these latches are unintentional and caused by incomplete assignments to variables in conditional or case statements. In a few cases, Integrated Synthesis may extract false latches for some conditional statements. For example, in the following always construct, the conditional statement tests for both sel == 1'b1 and sel == 1'b0.

always_comb
begin
	if(sel == 1'b1)
 		o = a;
	else if(sel == 1'b0)
 		o = b;
end

            

Integrated Synthesis will infer a latch for o initially. Later on, during optimization, Integrated Synthesis will remove the latch as unnecessary. However, Intel advises against such descriptions. During simulation, o behaves as a latch when sel == 1'bx, which may result in a mismatch between the simulated behavior of the design and the synthesized netlist.