ID:10165 SystemVerilog RTL Coding error at <location>: always_latch construct does not infer latched logic

CAUSE: In an always construct at the specified location in a Verilog Design File(.v), you indicated that you were describing latched logic by using the always_latch keyword. However, Integrated Synthesis did not infer latched logic when synthesizing the statements in this construct. You either described purely combinational logic in this construct, or you described latched behavior using a style that Integrated Synthesis could not recognize.

ACTION: If you intended to describe combinational logic, then use an always_comb construct. Otherwise, if you intended to describe latched logic, refer to the Quartus Prime Handbook for recommended coding styles that will infer latches.