ID:10868 Verilog HDL or VHDL XML Interface error at <location>: parameter or generic "<name>" has an unsupported type

CAUSE: You attempted to create an XML interface for an entity or module in a Verilog Design File (.v) or VHDL Design File (.vhd). However, the specified parameter or generic has an unsupported type.

ACTION: Use a supported type for the specified parameter or generic.