ID:10022 Can't use "<name>" as a pragma trigger for a synthesis attribute or directive when running in <name> mode

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used the specified pragma trigger for a synthesis directive or attribute, also commonly called pragmas. However, you also specified an EDA formal verification tool that does not recognize the specified pragma and, consequently, ignores the synthesis attribute or directive. As a result, your formal verification tool may report a mismatch between the synthesized netlist and your original HDL.

ACTION: Use a pragma trigger that is recognized by both Quartus Prime and your EDA formal verification tool. The Quartus Prime software recognizes altera, exemplar, synthesis, pragma, and synopsys as pragma triggers. You can also refrain from specifying an EDA formal verification tool in your project settings.