ID:13839 VHDL Loop Statement error at <location>: WHILE iteration scheme condition cannot contain signals, non-constant loop limit of <number> exceeded

CAUSE: In a Loop Statement at the specified location in a VHDL Design File (.vhd), you used a WHILE iteration scheme condition that contains one or more signals. However, the condition must be an expression of integer variables that contains no signals.

ACTION: Remove any signals from the WHILE iteration scheme condition.