ID:13940 VHDL Wait Statement error at <location>: Condition Clause for Wait Statement should not evaluate to a constant TRUE or FALSE

CAUSE: In an Wait Statement at the specified location in a VHDL Design File (.vhd), you used a Condition Clause that evaluates to a constant TRUE or FALSE. Quartus Prime Integrated Synthesis cannot create logic to match the simulated behavior of this Wait Statement. For example, in the following VHDL code, the Process Statement contains a Wait Statement that waits until the signal clk has the value '1'. However, because the signal has no value assignment, clk always has the default value '1'. Consequently, the condition clk = '1' always evaluates to TRUE.

signal clk : std_logic := '1'; -- Assume clk has no value assignment. 
 
               
process 
begin 
wait until clk = '1'; 
q <= d; 
end process;