ID:13626 VHDL Interface Declaration error in <location>: interface object "<name>" of mode out cannot be read. Change object mode to buffer.

CAUSE: In an Interface Declaration at the specified location in a VHDL design file (.vhd), you declared the specified interface object with a mode of Out. Integrated Synthesis attempted to read the value of the interface object, but cannot do so because the interface object has the mode Out.

ACTION: Change the mode of the interface object to buffer, or use a temporary internal object for the interface object. The following example shows how you can use a temporary internal object:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
               
ENTITY example IS
   PORT
   (
      ena   : IN   BIT;
      i     : IN   BIT;
      o     : OUT  BIT
   );
END example;
 
               
ARCHITECTURE a OF example IS
   SIGNAL tmp : BIT;
BEGIN
   PROCESS (ena, i)
   BEGIN
      CASE ena IS
         WHEN '1' =>
            tmp  <= i;
         WHEN OTHERS =>
            tmp  <= tmp;
      END CASE;
   END PROCESS;
   o <= tmp;
END a;