ID:13706 VHDL Event Expression error at <location>: can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S

CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to test for a clock edge by combining an S'EVENT with another expression that does not refer to the signal or variable S. Here, S represents the signal or variable in your event expression. To form a clock edge, you must combine S'EVENT with an expression that depends only on S. For example, the if statement in the following code contains a clocking condition that Quartus Prime Integrated Synthesis cannot synthesize because it contains an event expression with the signal ffclk and another expression with the signal ffin:

myrff : PROCESS (RST, CLK, EN)
BEGIN
   IF RST = '1' THEN
      Q <= '0';
   ELSIF CLK'EVENT AND EN = '1' THEN
      Q <= D;
   END IF;
END PROCESS;

ACTION: Rewrite the condition so it combines S'EVENT with an expression such as S = '1' or S = '0'. For the previous example, the correct code is:

myrff : PROCESS (RST, CLK, EN)
BEGIN
   IF RST = '1' THEN
      Q <= '0';
   ELSIF CLK'EVENT and CLK = '1' and EN = '1' THEN
      Q <= D;
   END IF;
END PROCESS;