ID:13939 VHDL Case Statement or If Statement error at <location>: can't synthesize condition that contains an isolated 'EVENT predefined attribute

CAUSE: In a Case Statement or If Statement at the specified location in a VHDL Design File (.vhd), you used an isolated 'EVENT predefined attribute on a variable or signal, that is, you did not combine the predefined attribute with another, level-test condition to form an explicit clock edge. Quartus Prime Integrated Synthesis cannot synthesize conditions based on isolated 'EVENT predefined attributes. For example, in the following code, an If Statement uses an isolated 'EVENT predefined attribute to test for an event on the signal clk:

my_dff : PROCESS (clk, rst)
BEGIN
   IF rst = '1' THEN
      q <= '0';
   ELSIF clk'EVENT THEN
      q <= data;
   END IF;
END PROCESS;

The Process Statement containing the If Statement may be attempting to create a register that is sensitive to both the positive and negative edges of clk. However, Quartus Prime Integrated Synthesis cannot generate logic to implement a dual-edge register in a device.

ACTION: Modify the Case or If Statement so that it represents a valid clock edge, or remove the isolated 'EVENT predefined attribute. For the previous example, you can rewrite the If Statement so that it infers a positive edge-triggered register:

my_dff : PROCESS (clk, rst)
BEGIN
   IF rst = '1' THEN
      q <= '0';
   ELSIF clk'EVENT and clk = '1' THEN
      q <= data;
   END IF;
END PROCESS;