ID:13787 VHDL error at <location>: "<name>" is not synthesizable since "<name>" does not hold its value under NOT(clock-edge) condition

CAUSE: In a VHDL Design File (.vhd) at the specified location, you attempted to infer a register for the specified signal. However, you assigned a value to the signal on a clock edge, and then you assigned a value to the signal outside this clock edge (this second value assignment may be triggered by a different clock edge or by an asynchronous condition). For example, the If Statement in the following code assigns one value to the signal state on the clock edge, and then assigns another value to state outside the clock edge:

PROCESS(clk)
BEGIN
   IF falling_edge(clk) THEN 
      state <= write;
   ELSE
      state <= idle; 
   END IF;
END PROCESS

Because the signal does not hold its value outside its controlling clock edge, Quartus Prime Integrated Synthesis cannot infer a register for the signal that matches the simulated behavior of the design.

ACTION: To infer a register for a signal, do not assign a value to the signal after you've specified its synchronous behavior. Instead, to model the correct precedence between synchronous and asynchronous value assignments, specify the signal's asynchronous behavior first and its synchronous behavior last. For the previous example, you can use the following code:

PROCESS(rst,clk)
BEGIN
   IF rst='1' THEN 
      state <= idle; 
   ELSIF falling_edge(clk) THEN
      state <= write;
   END IF;
END PROCESS