ID:13661 VHDL Association List error at <location>: formal "<name>" does not exist

CAUSE: In an association list at the specified location in a VHDL Design File (.vhd), you associated an actual with the specified formal of an object such as component, entity, or subprogram. However, the object has no such formal port or parameter. For example, the association list in the following code assigns the actual parameter i to the formal port i of the component dff, but the component declaration for dff does not declare a formal port i:

ENTITY err IS
   PORT
   (
      clk   : IN   BIT;
      i     : IN   BIT;
      o     : OUT  BIT
    );
END err;
	
               
ARCHITECTURE a OF err IS
   COMPONENT dff
      PORT (d, clk : IN  BIT;
            q      : OUT BIT);
   END COMPONENT;
BEGIN
   dff1 : dff PORT MAP (i=>i, q=>o, clk=>clk);
END a;

You must declare a formal port or parameter before you associate an actual with it.