ID:13710 VHDL Type Conversion error at <location>: cannot convert formal type "<name>" to actual type "<name>"

CAUSE: In a type conversion at the specified location in a VHDL design file (.vhd), you attempted to convert from the specified formal type to the specified actual type. However, you cannot convert between the formal and actual types because the types are not closely related.

ACTION: Implement an explicit function to convert the types, or modify one or both types to make them closely related.