ID:13933 VHDL error at <location>: can't implement clock enable condition because clock enable signals are combined using binary operator "<name>"

CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to specify an enable condition for a clock edge by merging two enable signals. However, Quartus Prime Integrated Synthesis cannot infer a register to implement the clock enable condition because you attempted to merge the two enable signals using the specified binary operator, which is not AND, OR, or XOR. You must combine the enable signals only with a binary AND, OR, or XOR.

ACTION: Change the expression so it uses the binary AND, OR, or XOR operator to combine enable signals. In most cases, you can improve the readability of an expression by grouping the enable signals into a single enable condition before specifying the enable condition for a clock edge using a binary AND operator. For example, in the following code, expressions correctly combine enable signals using a binary AND or XOR (the comments in the following code show how to improve readability by grouping enable signals before combining the enable signals with a clock edge):

PROCESS (clk)
BEGIN
    -- Clock enable condition = (en1 AND en2)
     IF((rising_edge(clk) AND en1) AND (rising_edge (clk) AND en2) THEN
        q1 <= data;
    END IF;
    -- You can also specify the previous clock enable condition as
	-- IF(rising_edge(clk) AND (en1 AND en2)) THEN
    --    q1 <= data;
    -- END IF;
    -- Clock enable condition = (en1 XOR en2)
    IF((rising_edge(clk) AND en1) XOR (rising_edge(CLK) AND en2)) THEN
        q2 <= data;
    END IF;
    -- You can also specify the previous clock enable condition as 
    -- IF(rising_edge(clk) AND (en1 XOR en2)) THEN
    --    q2 <= data;
    -- END IF;
END PROCESS;