ID:13850 VHDL Assertion Statement at <location>: assertion is false - report <text> (FAILURE or ERROR)

CAUSE: In an assertion statement at the specified location in a VHDL design file (.vhd), you used an assertion expression that evaluates to False. The specified text contains the report string associated with the assertion.

ACTION: Change your design so that the assertion expression evaluates to True, or remove the assertion from your design altogether.