ID:17703 VHDL error at <location>: case expression type of matching case is not a bit or a std_ulogic or 1-dimensional array of bit/std_ulogic

CAUSE: Quartus Prime Integrated Synthesis generated the specified error message for the specified location in a Design File.

ACTION: Fix the problem identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this error message.