ID:13501 Verilog HDL literal error at <location>: a sized number cannot have zero size

CAUSE: In an expression at the specified location in a Verilog Design File (.v), you used a sized number (a literal). However, you specified a size that is zero, for example 0'b101. Verilog HDL does not allow you to specify zero as the size of a literal.

ACTION: Specify a non-zero size.