ID:13235 Verilog HDL unsupported feature error at file "<name>" (line <number>): cannot synthesize MOS switch gate primitive

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated a nmos, pmos, or cmos MOS switch gate primitive. However, the Quartus Prime software does not support synthesis of MOS switch gate primitives.

ACTION: Edit the design to remove all MOS switch gate primitives. You can replace them with behavioral models of the basic gates, or you can rewrite the design in a behavioral style.