ID:13486 Verilog HDL Unsupported Feature error at <location>: can't synthesize cross-hierarchy defparam "<name>" on instance "<name>"

CAUSE: In a defparam statement at the specified location in a Verilog Design File (.v), you used the specified defparam to override a parameter on a target instance that was instantiated inside another instance in the current hierarchy. Such defparams are referred to as cross-hierarchy defparams because they do not override a parameter on an instance that was directly instantiated by the current hierarchy. Though Verilog HDL supports cross-hierarchy defparams, Quartus Prime Integrated Synthesis does not. All defparams in a defparam statement must override parameters on instances that are directly instantiated by the module containing the defparam statement.

ACTION: Override the parameter value using a defparam statement in the module that contains the target instance.