ID:13498 Verilog HDL error at <location>: unsized constants are not allowed in concatenations

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), one of the expressions in a concatenation operator has evaluated to a constant, integer or real. The Verilog language reference manual does not allow unsized constants in concatenations. For example, the following two concatenations are both illegal:

               
reg [3:0]o;
reg [3:0]o2;
assign o = {1,1,1,1};
assign o2 = {4{1}};

            

ACTION: Change the erroneous expression so that it no longer evaluates to an unsized constant. For example, here is the corrected version of the above example:

               
reg [3:0]o;
reg [3:0]o2;
assign o = {1'b1,1'b1,1'b1,1'b1};
assign o2 = {4{1'b1}};