ID:13464 Verilog HDL syntax error at <location>: experienced unexpected end-of-file while processing comment block -- comment block must have ending comment delimiter (asterisk and slash)

CAUSE: In a block comment in a Verilog Design File (.v) at the specified location, you used a beginning comment delimiter (slash and asterisk, or /*) without a corresponding ending comment delimiter (asterisk and slash, or */). As a result, Quartus Prime Integrated Synthesis unexpectedly reached the end-of-file marker and consequently disabled further processing of the file.

ACTION: Add a */ at the end of the comment block that begins with the unmatched /*.