ID:13395 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: sequential table entry "<text>" found in combinational table

CAUSE: In a user-defined primitive (UDP) declaration at the specified location in a Verilog Design File (.v), you used a UDP table; however, the UDP table, which Quartus Prime Integrated Synthesis has identified as modeling combinational logic, has a table entry for modeling sequential logic.

ACTION: Change the UDP table to be either entirely combinational, or entirely sequential.