ID:13379 Verilog HDL error at <location>: parameter "<name>" is not a formal parameter of instantiated module

CAUSE: In a Verilog Design File (.v) at the specified location, you used a Defparam Statement or a named Module Instance Parameter Value Assignment list to change the value of a parameter in a module that you are instantiating. However, the specified parameter does not exist in the instantiated module. This error may occur if you have mistyped the parameter name.

ACTION: Carefully check the names in the Parameter Value Assignment Statement and in the instantiated module to make sure they match.