ID:13369 Verilog HDL Loop Statement error at <location>: loop with non-constant loop condition must terminate within <number> iterations

CAUSE: In a loop statement at the specified location in a Verilog Design File (.v), you specified a loop condition that does not evaluate to constant true or false on each loop iteration. For example, it may depend on an input to your module. Quartus Prime Integrated Synthesis continued to execute the loop for the specified number of iterations, but the loop did not terminate. To avoid an infinite loop, Integrated Synthesis prematurely terminated the synthesis of your design.

ACTION: Modify the loop condition so that it evaluates to a constant true or false within the specified number of iterations. You can also use a disable (Verilog) or break statement (SystemVerilog). If your loop requires more iterations to terminate successfully, increase the loop limit with the VERILOG_NON_CONSTANT_LOOP_LIMIT logic option.