ID:13521 Verilog HDL Port Declaration error at <location>: cannot redeclare port "<name>" because it is already fully declared

CAUSE: In a Verilog Design File (.v), you redeclared the specified port. However, you already declared both the port and its type, either in a single Port Declaration or in separate Port and Net or Variable Declarations. Once you have declared a type for the port, you cannot redeclare it.

ACTION: Remove the illegal redeclaration for the specified port.