ID:13399 Verilog HDL Generate Statement error at <location>: variable "<name>" is not declared as genvar

CAUSE: In a Generate Statement at the specified location in a Verilog Design File (.v), you used a name that is not is not declared as a Generate Statement index variable, or genvar. An index variable that is used to control a Generate Statement must be declared as a genvar. You cannot use other data types as Generate Loop variables.

ACTION: Make sure each variable used to control a Generate Statement is declared as a genvar.