ID:13327 Verilog HDL Always Construct error at <location>: Forever Statement is not supported in Always Construct

CAUSE: In an Always Construct at the specified location in a Verilog Design File (.v), you used a Forever Statement. However, although Forever Statements are supported in both Always Constructs and Initial Constructs in Verilog HDL, the Quartus Prime software supports Forever Statements only in Initial Constructs.

ACTION: Move the Forever Statement from the Always Construct to an Initial Construct, or replace the Forever Statement in the Always Construct with one of the other types of Looping Statements.