ID:13532 Verilog HDL Object Declaration error at <location>: can't declare implicit net "<name>" because the current value of 'default_nettype is "none"

CAUSE: At the specified location in a Verilog Design File (.v), you referred to the specified net, which has no explicit declaration and must be implicitly declared with the net type specified in the 'default_nettype directive. However, implicit net declarations are disabled because the current value of the 'default_nettype directive is none.

ACTION: Declare the net explicitly or specify a value other than none for the 'default_nettype directive.