ID:13496 Verilog HDL Module Instantiation error at <location>: port "<port name>" on instance "<instance name>" has width <number>, but the same port on prior instances in the array had width <number>

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated an array of instances. However, the specified port on the specified instance has a different width than the same port on prior instances in the array. The special port connection rules defined by Verilog HDL require that all instances in the array have consistent widths for all ports.

ACTION: Check your parameter overrides instance in the array. In particular, look for Defparam Statements that might alter the port widths in instantiated module. Remove or modify the Defparam Statements to achieve a consistent width for the specified port in all instances in the array.