ID:18469 Verilog HDL error at <location>: checker body cannot have always_ff/always_comb/always_latch/final construct in SystemVerilog 1800-2009 dialect

CAUSE: Quartus Prime Integrated Synthesis generated the specified error message for the specified location in a Design File.

ACTION: Fix the problem identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this error message.