ID:17522 Verilog HDL error at <location>: width of actual <number> differs from expected width of formal <number> or <number> for port <string>

CAUSE: Quartus Prime Integrated Synthesis generated the specified error message for the specified location in a Design File.

ACTION: Fix the problem identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this error message.