ID:17430 Verilog HDL error at <location>: number of unpacked dimensions <number> does not match the number of dimensions <number> of VHDL unconstrained array

CAUSE: Quartus Prime Integrated Synthesis generated the specified error message for the specified location in a Design File.

ACTION: Fix the problem identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this error message.