ID:13264 Can't resolve multiple constant drivers for net "<name>" at <location>

CAUSE: In the current design, multiple constant (non-tri-state) drivers are contending for the specified net, which was created by Quartus Prime Integrated Synthesis to represent one or more signals. This condition usually occurs when a Verilog Design File (.v) or VHDL Design File (.vhd) contains multiple concurrent assignments to the same signal. Quartus Prime Integrated Synthesis attempted to resolve the electrically equivalent assignments, but cannot resolve the contending assignments into a single equivalent driver. The message(s) immediately below this message indicate the constant drivers to the net that conflict with the net's first constant driver. This signal might be replicated by a generate for-loop.

ACTION: Check the design for multiple concurrent assignments to the same signal.