ID:13558 SystemVerilog Declaration error at <location>: prefix for packed array type does not refer to a packable type

CAUSE: In a declaration at the specified location in a Verilog Design File(.v), you declared a packed array type with an unpackable prefix. For example, in the following code fragment, the prefix is a type name that was declared as a packed array type in a type declaration.

typedef bit [7:0] byte_t;

               
byte_t [3:0] foo; // byte_t is already a packed array type!