ID:13588 SystemVerilog error at <location>: <name> type and <name> type are not equivalent - <string>

CAUSE: In an expression, assignment, port connection, or argument binding, you used two objects with the specified types. Based on the context, SystemVerilog requires the objects to have equivalent types, but these two types are not equivalent for the reason(s) listed in the message. Equivalent type compatibility allows more flexibility than the matching types. Enums and unpacked structs are only equivalent to themselves. That is, an enum type from one declaration can never match an enum type from another declaration. Unpacked arrays only match unpacked arrays with the same number of unpacked dimensions, the same number of elements in each dimension, and with matching element types. Packed arrays and other integral types match only if they have the same total number of bits, signing, and two-state or four-state logic types.

ACTION: Modify your HDL source to remove the type error. You may need to modify your expression or the declarations of the objects themselves.