ID:13589 SystemVerilog error at <location>: <name> type cannot be assigned to <name> type - <string>

CAUSE: In an assignment, port connection, or argument binding, you attempted to assign types that are not assignment compatible. Enums and unpacked struct targets must be assigned expressions with the matching type unless you use a type cast. Unpacked arrays must also be assigned values with the same number of unpacked dimensions, the same number of elements in each unpacked dimension, and assignment-compatible element types. Integral types such as packed arrays, integers, and single-bit types may be assigned to each other freely.

ACTION: Modify your HDL source to remove the type error. You may need to modify your expression or the declarations of the objects themselves.