ID:13559 SystemVerilog Operator error at <location>: can't use operator "<name>" outside a procedural statement

CAUSE: In an expression at the specified location in a Verilog Design File(.v), you used the specified operator, which is legal only inside a procedural statement such as an always construct or function. However, you used the operator in a continuous assignment, variable declaration assignment, or other illegal context.

ACTION: Remove the operator from the expression, or enclose the expression in a procedural statement.