ID:13576 SystemVerilog Type Cast error at <location>: the source and destination types must have the same number of bits when casting to or from an unpacked bitstream type

CAUSE: At the specified location in a Verilog Design File (.v), you converted an expression to a specific destination type using a cast. However, the source and destination types do not have the same number of bits, and the unpacked bitstream type is one of the types. When converting to or from an unpacked bitstream type, the SystemVerilog design file (.sv) requires that both the source and destination types produce a bit-stream with the same number of bits.

ACTION: Check the source and destination types in your type cast. If necessary, modify one or both types so that both produce bitstreams with the same number of bits. If necessary, add additional type casts to adjust the type of the expression accordingly.