ID:13570 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance "<string>" because the instance has no module binding

CAUSE: In a SystemVerilog Design File (.sv) at the specified location, you connected a port on an instance to an expression with an aggregate value. For example, the expression refers to an unpacked array, struct, or interface. When resolving this port connection, Quartus Prime Integrated Synthesis requires the declaration for the instantiated module. Otherwise, Integrated Synthesis cannot verify that the actual data type of the expression is compatible with the formal data type of the port. Integrated Synthesis does not require the module declaration if an instance has port connections to integral expressions such as those involving only packed arrays, packed structs, or scalars. These expressions are usually compatible with the underlying formal port, unless the formal port itself has an aggregate data type. If such a mismatch occurs, Integrated Synthesis will report it when merging hierarchies.

ACTION: Add the file containing the module declaration (or an equivalent extern module declaration) to your Quartus Prime project. If you are instantiating a VHDL entity, you must create an equivalent extern module declaration to function as a Verilog prototype for the VHDL entity.