ID:13243 Verilog HDL XML Interface error at <location>: list of ports for module "<name>" contains unsupported port expression(s)

CAUSE: You attempted to create an XML interface for the specified module in a Verilog Design File (.v). However, the module's list of ports has an indexed name, slice, or explicit port. The Quartus Prime software can generate an XML interface only for list of ports expressions that are simple identifiers.

ACTION: Use only simple identifiers in the module's list of ports.